/*******************************************************************************
* Copyright (C) 2019 China Micro Semiconductor Limited Company. All Rights Reserved.
*
* This software is owned and published by:
* CMS LLC, No 2609-10, Taurus Plaza, TaoyuanRoad, NanshanDistrict, Shenzhen, China.
*
* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
*
* This software contains source code for use with CMS
* components. This software is licensed by CMS to be adapted only
* for use in systems utilizing CMS components. CMS shall not be
* responsible for misuse or illegal use of this software for devices not
* supported herein. CMS is providing this software "AS IS" and will
* not be responsible for issues arising from incorrect user implementation
* of the software.
*
* This software may be replicated in part or whole for the licensed use,
* with the restriction that this Disclaimer and Copyright notice must be
* included with each copy of this software, whether used in part or whole,
* at all times.
*/

/*****************************************************************************/
/** \file cms32m56xxx.h
**
**
** History:
** 
*****************************************************************************/
#ifndef __CMS32F0301_H__
#define __CMS32F0301_H__

#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************/
/* Include files */
/*****************************************************************************/

/*****************************************************************************/
/* Global pre-processor symbols/macros ('#define') */
/*****************************************************************************/
/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */
typedef enum IRQn
{
/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
	NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                      */
	HardFaULt_IRQn                = -13,      /*!<  3 Hard FaULt Interrupt                        */
	SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                           */
	PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                           */
	SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                       */   
/******  CMS32F030x Specific Interrupt Numbers ****************************************************/
	GPIO0_IRQn           = 0,       		/*!< GPIO 0 Interrupt                                 */
	GPIO1_IRQn           = 1,     			/*!< GPIO 1 Interrupt                                 */
	GPIO2_IRQn           = 2,      			/*!< GPIO 2 Interrupt                                 */
	GPIO3_IRQn           = 3,      			/*!< GPIO 3 Interrupt                                 */
	GPIO4_IRQn           = 4,       		/*!< GPIO 4 Interrupt                                 */	
	CCP_IRQn             = 6,       		/*!< Capture/PWM Interrupt                            */

	WWDT_IRQn            = 9,      			/*!< WWDT    Interrupt     			                  */
	ADCB_IRQn            = 12,     			/*!< ADC B   Converter Interrupt                      */
	ACMP_IRQn            = 13,       		/*!< ACMP    Interrupt 			                      */
	UART0_IRQn           = 15,       		/*!< UART0   Interrupt 			                      */
	UART1_IRQn           = 16,      		/*!< UART1   Interrupt  			                  */
	TMR0_IRQn            = 19,     			/*!< timer 0 Interrupt     			                  */
	TMR1_IRQn            = 20,      		/*!< timer 1 Interrupt         			              */
	TMR2_IRQn            = 21,     			/*!< timer 2 Interrupt     			                  */
	TMR3_IRQn            = 22,      		/*!< timer 3 Interrupt         			              */
	WDT_IRQn             = 23,       		/*!< WDT  	 Interrupt                     			  */
	I2C_IRQn             = 24,     			/*!< I2C 	 Interrupt                     			  */
	SPI_IRQn             = 26,       		/*!< SSP/SPI  	 Interrupt                     		  */
	LVD_IRQn             = 31,       		/*!< LVD	 Interrupt                    			  */   
} IRQn_Type;

/* ================================================================================ */
/* ================      Processor and Core Peripheral Section     ================ */
/* ================================================================================ */

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/* --------  Configuration of Core Peripherals  ----------------------------------- */
#define __CM0PLUS_REV             0x0001U   /* Core revision r0p1 */
#define __MPU_PRESENT             0U        /* no MPU present */
#define __VTOR_PRESENT            0U        /* no VTOR present */
#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */

#include "core_cm0plus.h"
#include "system_cms32f0301.h"


#ifndef NULL
	#define NULL 0
#endif

/*---------------------- System Manger Controller -------------------------*/
typedef struct
{
	__I  uint32_t DID;					
	__IO uint32_t AHBCKDIV;				
	__IO uint32_t APBCKDIV;				
	__IO uint32_t APBCKEN;
	__IO uint32_t CLKODIV;
	__IO uint32_t PCON;
	__O	 uint32_t RSTCON;
	__IO uint32_t RSTSTAT;
	__IO uint32_t CLKCON;
	__IO uint32_t CLKSEL;
	__I	 uint32_t CLKSTAT;
	
	__I  uint32_t RESERVE0;
	
	__I	 uint32_t IOMUX;
	__I  uint32_t CIDL;
	__I  uint32_t CIDH;
	__IO uint32_t LVDCON;
	__IO uint32_t IOP00CFG;
	__IO uint32_t IOP01CFG;	
	
	__I  uint32_t RESERVE1;
	__I  uint32_t RESERVE2;
	
	__IO uint32_t IOP04CFG;	
	__IO uint32_t IOP05CFG;	
	__IO uint32_t IOP06CFG;	
	__IO uint32_t IOP07CFG;	
	__IO uint32_t IOP10CFG;	
	
	__I uint32_t RESERVE3;
	
	__IO uint32_t IOP12CFG;	
	__IO uint32_t IOP13CFG;	
	__IO uint32_t IOP14CFG;	
	__IO uint32_t IOP15CFG;	
	__IO uint32_t IOP16CFG;
	__IO uint32_t IOP17CFG;	
	
	__I uint32_t  RESERVE4;	
	
	__IO uint32_t IOP21CFG;	
	__IO uint32_t IOP22CFG;	
	__IO uint32_t IOP23CFG;	
	__IO uint32_t IOP24CFG;	
	__IO uint32_t IOP25CFG;	
	__IO uint32_t IOP26CFG;	
	
	__I uint32_t  RESERVE5;
	
	__IO uint32_t IOP30CFG;	
	__IO uint32_t IOP31CFG;	
	__IO uint32_t IOP32CFG;	
	
	__I uint32_t  RESERVE6;
	
	__IO uint32_t IOP34CFG;	
	__IO uint32_t IOP35CFG;	
	__IO uint32_t IOP36CFG;	
	
	__I uint32_t  RESERVE7;
	
	__IO uint32_t IOP40CFG;	
	
	__I uint32_t  RESERVE8;
	__I uint32_t  RESERVE9;
	
	__IO uint32_t IOP43CFG;		
	__IO uint32_t IOP44CFG;
	
	__I uint32_t  RESERVE10;
	
	__IO uint32_t IOP46CFG;		
	__IO uint32_t IOP47CFG;
		
	__I uint32_t  RESERVE11[8];
	
	__IO uint32_t IMSC;		
	__I  uint32_t RIS;	
	__I  uint32_t MIS;	
	__O  uint32_t ICLR;		
	__I  uint32_t RESERVE12[40];
	__IO uint32_t SRAMLOCK;	
	__I  uint32_t RESERVE13[3];
	__IO uint32_t GPIO0LOCK;	
	__IO uint32_t GPIO1LOCK;
	__IO uint32_t GPIO2LOCK;
	__IO uint32_t GPIO3LOCK;
	__IO uint32_t GPIO4LOCK;	
	__I  uint32_t RESERVE14[10];
	__IO uint32_t IOCFGLOCK;
} SYS_T;


/*------AHBCKDIV------------------------------------------------------------*/
#define	SYS_AHBCKDIV_AHBDIV_Pos		(0)
#define SYS_AHBCKDIV_AHBDIV_Msk		(0xffUL<<SYS_AHBCKDIV_AHBDIV_Pos)
/*------APBCKDIV------------------------------------------------------------*/
#define	SYS_APBCKDIV_APBDIV_Pos		(0)
#define SYS_APBCKDIV_APBDIV_Msk		(0xffUL<<SYS_APBCKDIV_APBDIV_Pos)
/*------APBCKEN-------------------------------------------------------------*/
#define	SYS_APBCKEN_ADCBCE_Pos		(27)
#define SYS_APBCKEN_ADCBCE_Msk		(0x1UL<<SYS_APBCKEN_ADCBCE_Pos)
#define	SYS_APBCKEN_ACMPCE_Pos		(26)
#define SYS_APBCKEN_ACMPCE_Msk		(0x1UL<<SYS_APBCKEN_ACMPCE_Pos)
#define	SYS_APBCKEN_CRCCE_Pos		(20)
#define SYS_APBCKEN_CRCCE_Msk		(0x1UL<<SYS_APBCKEN_CRCCE_Pos)
#define	SYS_APBCKEN_WWDTCE_Pos		(14)
#define SYS_APBCKEN_WWDTCE_Msk		(0x1UL<<SYS_APBCKEN_WWDTCE_Pos)
#define	SYS_APBCKEN_CCPCE_Pos		(12)
#define SYS_APBCKEN_CCPCE_Msk		(0x1UL<<SYS_APBCKEN_CCPCE_Pos)
#define	SYS_APBCKEN_SPPCE_Pos		(9)
#define SYS_APBCKEN_SPPCE_Msk		(0x1UL<<SYS_APBCKEN_SPPCE_Pos)
#define	SYS_APBCKEN_I2CCE_Pos		(7)
#define SYS_APBCKEN_I2CCE_Msk		(0x1UL<<SYS_APBCKEN_I2CCE_Pos)
#define	SYS_APBCKEN_TIMER23CE_Pos	(6)
#define SYS_APBCKEN_TIMER23CE_Msk	(0x1UL<<SYS_APBCKEN_TIMER23CE_Pos)
#define	SYS_APBCKEN_UART1CE_Pos		(4)
#define SYS_APBCKEN_UART1CE_Msk		(0x1UL<<SYS_APBCKEN_UART1CE_Pos)
#define	SYS_APBCKEN_UART0CE_Pos		(3)
#define SYS_APBCKEN_UART0CE_Msk		(0x1UL<<SYS_APBCKEN_UART0CE_Pos)
#define	SYS_APBCKEN_DIVCE_Pos	(2)
#define SYS_APBCKEN_DIVCE_Msk	(0x1UL<<SYS_APBCKEN_DIVCE_Pos)
#define	SYS_APBCKEN_TIMER01CE_Pos	(1)
#define SYS_APBCKEN_TIMER01CE_Msk	(0x1UL<<SYS_APBCKEN_TIMER01CE_Pos)
#define	SYS_APBCKEN_WDTCE_Pos		(0)
#define SYS_APBCKEN_WDTCE_Msk		(0x1UL<<SYS_APBCKEN_WDTCE_Pos)
/*------CLKODIV-----------------------------------------------------------*/
#define	SYS_CLKODIV_CLKSEL_Pos		(9)
#define SYS_CLKODIV_CLKSEL_Msk		(0x3UL<<SYS_CLKODIV_CLKSEL_Pos)
#define	SYS_CLKODIV_EN_Pos			(8)
#define SYS_CLKODIV_EN_Msk			(0x1UL<<SYS_CLKODIV_EN_Pos)
#define	SYS_CLKODIV_DIV_Pos			(0)
#define SYS_CLKODIV_DIV_Msk			(0xffUL<<SYS_CLKODIV_DIV_Pos)
/*------PCON--------------------------------------------------------------*/
#define	SYS_PCON_KEY_Pos			(16)
#define SYS_PCON_KEY_Msk			(0xffffUL<<SYS_PCON_KEY_Pos)
#define	SYS_PCON_LDODS_Pos			(3)
#define SYS_PCON_LDODS_Msk			(0x1UL<<SYS_PCON_LDODS_Pos)
#define	SYS_PCON_STOP_Pos			(2)
#define SYS_PCON_STOP_Msk			(0x1UL<<SYS_PCON_STOP_Pos)
#define	SYS_PCON_DEEPSLEEP_Pos		(1)
#define SYS_PCON_DEEPSLEEP_Msk		(0x1UL<<SYS_PCON_DEEPSLEEP_Pos)
#define	SYS_PCON_SLEEP_Pos			(0)
#define SYS_PCON_SLEEP_Msk			(0x1UL<<SYS_PCON_SLEEP_Pos)

/*------RSTSTAT-----------------------------------------------------------*/
#define	SYS_RSTSTAT_CPURS_Pos		(2)
#define SYS_RSTSTAT_CPURS_Msk		(0x1UL<<SYS_RSTSTAT_CPURS_Pos)
#define	SYS_RSTSTAT_MCURS_Pos		(1)
#define SYS_RSTSTAT_MCURS_Msk		(0x1UL<<SYS_RSTSTAT_MCURS_Pos)
#define	SYS_RSTSTAT_WDTRS_Pos		(0)
#define SYS_RSTSTAT_WDTRS_Msk		(0x1UL<<SYS_RSTSTAT_WDTRS_Pos)

/*------CLKCON-----------------------------------------------------------*/
#define	SYS_CLKCON_IRCEN_Pos		(3)
#define SYS_CLKCON_IRCEN_Msk		(0x1UL<<SYS_CLKCON_IRCEN_Pos)
#define	SYS_CLKCON_IRCSEL_Pos		(0)
#define SYS_CLKCON_IRCSEL_Msk		(0x3UL<<SYS_CLKCON_IRCSEL_Pos)

/*------CLKSEL-----------------------------------------------------------*/
#define	SYS_CLKSEL_CLKSEL_Pos		(0)
#define SYS_CLKSEL_CLKSEL_Msk		(0x3UL<<SYS_CLKSEL_CLKSEL_Pos)

/*------CLKSSTAT----------------------------------------------------------*/
#define	SYS_CLKSTAT_IRCSTB_Pos		(0)
#define SYS_CLKSTAT_IRCSTB_Msk		(0x1UL<<SYS_CLKSTAT_IRCSTB_Pos)

/*------IOMUX-------------------------------------------------------------*/
#define	SYS_IOMUX_RESETPORT_Pos		(10)
#define SYS_IOMUX_RESETPORT_Msk		(0x3UL<<SYS_IOMUX_RESETPORT_Pos)

/*------LVDCON------------------------------------------------------------*/
#define	SYS_LVDCON_LVDF_Pos			(5)
#define SYS_LVDCON_LVDF_Msk			(0x1UL<<SYS_LVDCON_LVDF_Pos)
#define	SYS_LVDCON_LVDE_Pos			(4)
#define SYS_LVDCON_LVDE_Msk			(0x1UL<<SYS_LVDCON_LVDE_Pos)
#define	SYS_LVDCON_LVDS_Pos			(0)
#define SYS_LVDCON_LVDS_Msk			(0x7UL<<SYS_LVDCON_LVDS_Pos)


/*------IMSC--------------------------------------------------------------*/
#define	SYS_IMSC_LVDIMSC_Pos		(4)
#define SYS_IMSC_LVDIMSC_Msk		(0x1UL<<SYS_IMSC_LVDIMSC_Pos)
/*------RIS---------------------------------------------------------------*/
#define	SYS_RIS_LVDRIS_Pos			(4)
#define SYS_RIS_LVDRIS_Msk			(0x1UL<<SYS_RIS_LVDRIS_Pos)
/*------MIS---------------------------------------------------------------*/
#define	SYS_MIS_LVDMIS_Pos			(4)
#define SYS_MIS_LVDMIS_Msk			(0x1UL<<SYS_MIS_LVDMIS_Pos)
/*------ICLR--------------------------------------------------------------*/
#define	SYS_ICLR_LVDICLR_Pos		(4)
#define SYS_ICLR_LVDICLR_Msk		(0x1UL<<SYS_ICLR_LVDICLR_Pos)


/*---------------------- GPIO Manger Controller -------------------------*/
typedef struct gpio_io_t{
	__IO uint32_t P0 :1;
	__IO uint32_t P1 :1;	
	__IO uint32_t P2 :1;
	__IO uint32_t P3 :1;
	__IO uint32_t P4 :1;
	__IO uint32_t P5 :1;
	__IO uint32_t P6 :1;
	__IO uint32_t P7 :1;
}gpio_io_do_t, gpio_io_di_t;

typedef struct
{					
	__IO uint32_t PMS;
	__IO uint32_t DOM;	
	union{	
	__IO uint32_t DO;
	gpio_io_do_t DO_f;	
		};
	union{
	__I  uint32_t DI;
	gpio_io_di_t DI_f;
		};
	__IO uint32_t IMSC;	
	__I  uint32_t RIS;
	__I  uint32_t MIS;
	__IO uint32_t ICLR;	
	__IO uint32_t ITYPE;	
	__IO uint32_t IVAL;
	__IO uint32_t IANY;	
	__IO uint32_t DIDB;
	__O  uint32_t DOSET;			
	__O  uint32_t DOCLR;
	__IO uint32_t DR;
	__IO uint32_t SR;
} GPIO_T;

/*------PSM-----------------------------------------------------------------*/
#define	GPIO_PMS_PMS7_Pos		(28)
#define GPIO_PMS_PMS7_Msk		(0x7UL<<GPIO_PMS_PMS7_Pos)
#define	GPIO_PMS_PMS6_Pos		(24)
#define GPIO_PMS_PMS6_Msk		(0x7UL<<GPIO_PMS_PMS6_Pos)
#define	GPIO_PMS_PMS5_Pos		(20)
#define GPIO_PMS_PMS5_Msk		(0x7UL<<GPIO_PMS_PMS5_Pos)
#define	GPIO_PMS_PMS4_Pos		(16)
#define GPIO_PMS_PMS4_Msk		(0x7UL<<GPIO_PMS_PMS4_Pos)
#define	GPIO_PMS_PMS3_Pos		(12)
#define GPIO_PMS_PMS3_Msk		(0x7UL<<GPIO_PMS_PMS3_Pos)
#define	GPIO_PMS_PMS2_Pos		(8)
#define GPIO_PMS_PMS2_Msk		(0x7UL<<GPIO_PMS_PMS2_Pos)
#define	GPIO_PMS_PMS1_Pos		(4)
#define GPIO_PMS_PMS1_Msk		(0x7UL<<GPIO_PMS_PMS1_Pos)
#define	GPIO_PMS_PMS0_Pos		(0)
#define GPIO_PMS_PMS0_Msk		(0x7UL<<GPIO_PMS_PMS0_Pos)
/*------DIDB---------------------------------------------------------------*/
#define	GPIO_DIDB_DBCK_Pos		(8)
#define GPIO_DIDB_DBCK_Msk		(0xfUL<<GPIO_DIDB_DBCK_Pos)	//0xf
#define	GPIO_DIDB_DIDB_Pos		(0)
#define GPIO_DIDB_DIDB_Msk		(0xffUL<<GPIO_DIDB_DIDB_Pos)

/*---------------------- WDT Manger Controller -------------------------*/
typedef struct
{					
	__IO uint32_t CON;
	__IO uint32_t LOAD;	
	__I  uint32_t VAL;
	__I  uint32_t RIS;
	__I  uint32_t MIS;
	__O  uint32_t ICLR;
	__I  uint32_t RESERVE8[314];
	__IO uint32_t LOCK;		

} WDT_T;
/*------WDTCON-------------------------------------------------------------*/
#define	WDT_WDTCON_DEBUG_Pos		(16)
#define WDT_WDTCON_DEBUG_Msk		(0x1UL<<WDT_WDTCON_DEBUG_Pos)
#define	WDT_WDTCON_WDTEN_Pos		(8)
#define WDT_WDTCON_WDTEN_Msk		(0xffUL<<WDT_WDTCON_WDTEN_Pos)
#define	WDT_WDTCON_WDTPRE_Pos		(2)
#define WDT_WDTCON_WDTPRE_Msk		(0x3UL<<WDT_WDTCON_WDTPRE_Pos)
#define	WDT_WDTCON_WDTIEN_Pos		(0)
#define WDT_WDTCON_WDTIEN_Msk		(0x1UL<<WDT_WDTCON_WDTIEN_Pos)
/*------WDTRIS-------------------------------------------------------------*/
#define	WDT_WDTRIS_WDTRIS_Pos		(0)
#define WDT_WDTRIS_WDTRIS_Msk		(0x1UL<<WDT_WDTRIS_WDTRIS_Pos)
/*------WDTMIS-------------------------------------------------------------*/
#define	WDT_WDTMIS_WDTMIS_Pos		(0)
#define WDT_WDTMIS_WDTMIS_Msk		(0x1UL<<WDT_WDTMIS_WDTMIS_Pos)

/*---------------------- WWDT Manger Controller -------------------------*/
typedef struct
{					
	__IO uint32_t CON;
	__IO uint32_t RL;	
	__I  uint32_t VAL;
	__I  uint32_t RIS;
	__I  uint32_t MIS;
	__O  uint32_t ICLR;		
} WWDT_T;
/*------WWDTCON------------------------------------------------------------*/
#define	WWDT_WWDTCON_DEBUG_Pos		(31)
#define WWDT_WWDTCON_DEBUG_Msk		(0x1UL<<WWDT_WWDTCON_DEBUG_Pos)
#define	WWDT_WWDTCON_CMPDAT_Pos		(16)
#define WWDT_WWDTCON_CMPDAT_Msk		(0x3fUL<<WWDT_WWDTCON_CMPDAT_Pos)
#define	WWDT_WWDTCON_PSCSEL_Pos		(4)
#define WWDT_WWDTCON_PSCSEL_Msk		(0xfUL<<WWDT_WWDTCON_PSCSEL_Pos)
#define	WWDT_WWDTCON_WWDTRF_Pos		(2)
#define WWDT_WWDTCON_WWDTRF_Msk		(0x1UL<<WWDT_WWDTCON_WWDTRF_Pos)
#define	WWDT_WWDTCON_WWDTIEN_Pos	(1)
#define WWDT_WWDTCON_WWDTIEN_Msk	(0x1UL<<WWDT_WWDTCON_WWDTIEN_Pos)
#define	WWDT_WWDTCON_WWDTEN_Pos		(0)
#define WWDT_WWDTCON_WWDTEN_Msk		(0x1UL<<WWDT_WWDTCON_WWDTEN_Pos)
/*------WWDTRIS-----------------------------------------------------------*/
#define	WWDT_WWDTRIS_WWDTRIS_Pos	(0)
#define WWDT_WWDTRIS_WWDTRIS_Msk	(0x1UL<<WWDT_WWDTRIS_WWDTRIS_Pos)
/*------WWDTMIS-----------------------------------------------------------*/
#define	WWDT_WWDTMIS_WWDTMIS_Pos	(0)
#define WWDT_WWDTMIS_WWDTMIS_Msk	(0x1UL<<WWDT_WWDTMIS_WWDTMIS_Pos)
/*------WWDTICLR----------------------------------------------------------*/
#define	WWDT_WWDTICLR_WWDTICLR_Pos	(0)
#define WWDT_WWDTICLR_WWDTICLR_Msk	(0x1UL<<WWDT_WWDTICLR_WWDTICLR_Pos)
/*---------------------- CRC Manger Controller -------------------------*/
typedef struct
{					
	__IO uint32_t CRCIN;
	__IO uint32_t CRCD;	
} CRC_T;
/*---------------------- DIV Manger Controller -------------------------*/
typedef struct
{					
	__IO uint32_t CON;
	__IO uint32_t ALUA;	
	__IO uint32_t ALUB;	
	__I  uint32_t RES0;	
	__I  uint32_t RES1;	
} DIV_T;
/*------DIVCON-------------------------------------------------------------*/
#define DIV_CON_READY_Pos		(3)
#define DIV_CON_READY_Msk		(0x1UL<<DIV_CON_READY_Pos)
#define DIV_CON_DIVBY0_Pos		(2)
#define DIV_CON_DIVBY0_Msk		(0x1UL<<DIV_CON_DIVBY0_Pos)
#define DIV_CON_SIGN_Pos		(1)
#define DIV_CON_SIGN_Msk		(0x1UL<<DIV_CON_SIGN_Pos)

/*---------------------- Timer  Manger Controller -------------------------*/
typedef struct
{					
	__IO uint32_t CON;
	__IO uint32_t LOAD;
	__IO uint32_t VAL;
	__IO uint32_t RIS;
	__IO uint32_t MIS;
	__IO uint32_t ICLR;
	__IO uint32_t BGLOAD;
} TMR_T;
/*------CON---------------------------------------------------------------*/
#define	TMR_CON_TMREN_Pos			(7)
#define TMR_CON_TMREN_Msk			(0x1UL<<TMR_CON_TMREN_Pos)
#define	TMR_CON_TMRMS_Pos			(6)
#define TMR_CON_TMRMS_Msk			(0x1UL<<TMR_CON_TMRMS_Pos)
#define	TMR_CON_TMRIE_Pos			(5)
#define TMR_CON_TMRIE_Msk			(0x1UL<<TMR_CON_TMRIE_Pos)
#define	TMR_CON_TMRPRE_Pos			(2)
#define TMR_CON_TMRPRE_Msk			(0x3UL<<TMR_CON_TMRPRE_Pos)
#define	TMR_CON_TMRSZ_Pos			(1)
#define TMR_CON_TMRSZ_Msk			(0x1UL<<TMR_CON_TMRSZ_Pos)
#define	TMR_CON_TMROS_Pos			(0)
#define TMR_CON_TMROS_Msk			(0x1UL<<TMR_CON_TMROS_Pos)
/*------RIS---------------------------------------------------------------*/
#define	TMR_RIS_RIS_Pos				(0)
#define TMR_RIS_RIS_Msk				(0x1UL<<TMR_RIS_RIS_Pos)
/*------MIS---------------------------------------------------------------*/
#define	TMR_MIS_MIS_Pos				(0)
#define TMR_MIS_MIS_Msk				(0x1UL<<TMR_MIS_MIS_Pos)
/*------ICLR--------------------------------------------------------------*/
#define	TMR_ICLR_ICLR_Pos			(0)
#define TMR_ICLR_ICLR_Msk			(0x1UL<<TMR_ICLR_ICLR_Pos)
/*---------------------- CCP  Manger Controller -------------------------*/
typedef struct
{					
	__IO uint32_t CON0;
	__IO uint32_t LOAD0;
	__IO uint32_t D0A;
	__IO uint32_t D0B;
	__IO uint32_t CON1;
	__IO uint32_t LOAD1;
	__IO uint32_t D1A;
	__IO uint32_t D1B;
	__I  uint32_t RESERVE0[8];
	__IO uint32_t IMSC;
	__I  uint32_t RIS;
	__I  uint32_t MIS;
	__O  uint32_t ICLR;
	__IO uint32_t RUN;
	__IO uint32_t LOCK;
	__IO uint32_t CAPCON;
	__IO uint32_t CAPCHS;	
	__IO uint32_t CAP0DAT;	
	__IO uint32_t CAP1DAT;	
	__IO uint32_t CAP2DAT;	
	__IO uint32_t CAP3DAT;	
} CCP_T;
/*------CCPCON0-------------------------------------------------------------*/
#define	CCP_CCPCON0_CCP0ZBEN_Pos	(9)
#define CCP_CCPCON0_CCP0ZBEN_Msk	(0x1UL<<CCP_CCPCON0_CCP0ZBEN_Pos)
#define	CCP_CCPCON0_CCP0ZAEN_Pos	(8)
#define CCP_CCPCON0_CCP0ZAEN_Msk	(0x1UL<<CCP_CCPCON0_CCP0ZAEN_Pos)
#define	CCP_CCPCON0_CCP0EN_Pos		(6)
#define CCP_CCPCON0_CCP0EN_Msk		(0x1UL<<CCP_CCPCON0_CCP0EN_Pos)
#define	CCP_CCPCON0_CCP0PS_Pos		(4)
#define CCP_CCPCON0_CCP0PS_Msk		(0x3UL<<CCP_CCPCON0_CCP0PS_Pos)
#define	CCP_CCPCON0_CCP0MS_Pos		(3)
#define CCP_CCPCON0_CCP0MS_Msk		(0x1UL<<CCP_CCPCON0_CCP0MS_Pos)
#define	CCP_CCPCON0_CCP0CM0CS_Pos	(2)
#define CCP_CCPCON0_CCP0CM0CS_Msk	(0x1UL<<CCP_CCPCON0_CCP0CM0CS_Pos)
#define	CCP_CCPCON0_CCP0CM0ES_Pos	(0)
#define CCP_CCPCON0_CCP0CM0ES_Msk	(0x3UL<<CCP_CCPCON0_CCP0CM0ES_Pos)
/*------CCPLOAD0------------------------------------------------------------*/
#define	CCP_CCPLOAD0_RELOAD_Pos		(16)
#define CCP_CCPLOAD0_RELOAD_Msk		(0x1UL<<CCP_CCPLOAD0_RELOAD_Pos)
#define	CCP_CCPLOAD0_LOAD_Pos		(0)
#define CCP_CCPLOAD0_LOAD_Msk		(0xffffUL<<CCP_CCPLOAD0_LOAD_Pos)
/*------CCPD0A--------------------------------------------------------------*/
#define	CCP_CCPD0A_PWM0AOP_Pos		(16)
#define CCP_CCPD0A_PWM0AOP_Msk		(0x1UL<<CCP_CCPD0A_PWM0AOP_Pos)
#define	CCP_CCPD0A_DATA_Pos			(0)
#define CCP_CCPD0A_DATA_Msk			(0xffffUL<<CCP_CCPD0A_DATA_Pos)
/*------CCPD0B--------------------------------------------------------------*/
#define	CCP_CCPD0B_PWM0BOP_Pos		(16)
#define CCP_CCPD0B_PWM0BOP_Msk		(0x1UL<<CCP_CCPD0B_PWM0BOP_Pos)
#define	CCP_CCPD0B_DATA_Pos			(0)
#define CCP_CCPD0B_DATA_Msk			(0xffffUL<<CCP_CCPD0B_DATA_Pos)

/*------CCPCON1-------------------------------------------------------------*/
#define	CCP_CCPCON1_CCP1ZBEN_Pos	(9)
#define CCP_CCPCON1_CCP1ZBEN_Msk	(0x1UL<<CCP_CCPCON1_CCP1ZBEN_Pos)
#define	CCP_CCPCON1_CCP1ZAEN_Pos	(8)
#define CCP_CCPCON1_CCP1ZAEN_Msk	(0x1UL<<CCP_CCPCON1_CCP1ZAEN_Pos)
#define	CCP_CCPCON1_CCP1EN_Pos		(6)
#define CCP_CCPCON1_CCP1EN_Msk		(0x1UL<<CCP_CCPCON1_CCP1EN_Pos)
#define	CCP_CCPCON1_CCP1PS_Pos		(4)
#define CCP_CCPCON1_CCP1PS_Msk		(0x3UL<<CCP_CCPCON1_CCP1PS_Pos)
#define	CCP_CCPCON1_CCP1MS_Pos		(3)
#define CCP_CCPCON1_CCP1MS_Msk		(0x1UL<<CCP_CCPCON1_CCP1MS_Pos)
#define	CCP_CCPCON1_CCP1CM0CS_Pos	(2)
#define CCP_CCPCON1_CCP1CM0CS_Msk	(0x1UL<<CCP_CCPCON1_CCP1CM0CS_Pos)
#define	CCP_CCPCON1_CCP1CM0ES_Pos	(0)
#define CCP_CCPCON1_CCP1CM0ES_Msk	(0x3UL<<CCP_CCPCON1_CCP1CM0ES_Pos)
/*------CCPLOAD1------------------------------------------------------------*/
#define	CCP_CCPLOAD1_RELOAD_Pos		(16)
#define CCP_CCPLOAD1_RELOAD_Msk		(0x1UL<<CCP_CCPLOAD1_RELOAD_Pos)
#define	CCP_CCPLOAD1_LOAD_Pos		(0)
#define CCP_CCPLOAD1_LOAD_Msk		(0xffffUL<<CCP_CCPLOAD1_LOAD_Pos)
/*------CCPD1A--------------------------------------------------------------*/
#define	CCP_CCPD1A_PWM1AOP_Pos		(16)
#define CCP_CCPD1A_PWM1AOP_Msk		(0x1UL<<CCP_CCPD1A_PWM1AOP_Pos)
#define	CCP_CCPD1A_DATA_Pos			(0)
#define CCP_CCPD1A_DATA_Msk			(0xffffUL<<CCP_CCPD1A_DATA_Pos)
/*------CCPD1B--------------------------------------------------------------*/
#define	CCP_CCPD1B_PWM1BOP_Pos		(16)
#define CCP_CCPD1B_PWM1BOP_Msk		(0x1UL<<CCP_CCPD1B_PWM1BOP_Pos)
#define	CCP_CCPD1B_DATA_Pos			(0)
#define CCP_CCPD1B_DATA_Msk			(0xffffUL<<CCP_CCPD1B_DATA_Pos)



/*------CCPIMSC--------------------------------------------------------------*/
#define	CCP_CCPIMSC_CAP3IMSC_Pos	(11)
#define CCP_CCPIMSC_CAP3IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP3IMSC_Pos)
#define	CCP_CCPIMSC_CAP2IMSC_Pos	(10)
#define CCP_CCPIMSC_CAP2IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP2IMSC_Pos)
#define	CCP_CCPIMSC_CAP1IMSC_Pos	(9)
#define CCP_CCPIMSC_CAP1IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP1IMSC_Pos)
#define	CCP_CCPIMSC_CAP0IMSC_Pos	(8)
#define CCP_CCPIMSC_CAP0IMSC_Msk	(0x1UL<<CCP_CCPIMSC_CAP0IMSC_Pos)
#define	CCP_CCPIMSC_PWMIMSC5_Pos	(5)
#define CCP_CCPIMSC_PWMIMSC5_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC5_Pos)
#define	CCP_CCPIMSC_PWMIMSC4_Pos	(4)
#define CCP_CCPIMSC_PWMIMSC4_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC4_Pos)
#define	CCP_CCPIMSC_PWMIMSC1_Pos	(1)
#define CCP_CCPIMSC_PWMIMSC1_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC1_Pos)
#define	CCP_CCPIMSC_PWMIMSC0_Pos	(0)
#define CCP_CCPIMSC_PWMIMSC0_Msk	(0x1UL<<CCP_CCPIMSC_PWMIMSC0_Pos)

/*------CCPRIS---------------------------------------------------------------*/
#define	CCP_CCPRIS_CAP3IRIS_Pos		(11)
#define CCP_CCPRIS_CAP3IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP3IRIS_Pos)
#define	CCP_CCPRIS_CAP2IRIS_Pos		(10)
#define CCP_CCPRIS_CAP2IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP2IRIS_Pos)
#define	CCP_CCPRIS_CAP1IRIS_Pos		(9)
#define CCP_CCPRIS_CAP1IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP1IRIS_Pos)
#define	CCP_CCPRIS_CAP0IRIS_Pos		(8)
#define CCP_CCPRIS_CAP0IRIS_Msk		(0x1UL<<CCP_CCPRIS_CAP0IRIS_Pos)
#define	CCP_CCPRIS_PWMRIS5_Pos		(5)
#define CCP_CCPRIS_PWMRIS5_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS5_Pos)
#define	CCP_CCPRIS_PWMRIS4_Pos		(4)
#define CCP_CCPRIS_PWMRIS4_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS4_Pos)
#define	CCP_CCPRIS_PWMRIS1_Pos		(1)
#define CCP_CCPRIS_PWMRIS1_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS1_Pos)
#define	CCP_CCPRIS_PWMRIS0_Pos		(0)
#define CCP_CCPRIS_PWMRIS0_Msk		(0x1UL<<CCP_CCPRIS_PWMRIS0_Pos)
/*------CCPMIS---------------------------------------------------------------*/
#define	CCP_CCPMIS_CAP3IMIS_Pos		(11)
#define CCP_CCPMIS_CAP3IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP3IMIS_Pos)
#define	CCP_CCPMIS_CAP2IMIS_Pos		(10)
#define CCP_CCPMIS_CAP2IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP2IMIS_Pos)
#define	CCP_CCPMIS_CAP1IMIS_Pos		(9)
#define CCP_CCPMIS_CAP1IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP1IMIS_Pos)
#define	CCP_CCPMIS_CAP0IMIS_Pos		(8)
#define CCP_CCPMIS_CAP0IMIS_Msk		(0x1UL<<CCP_CCPMIS_CAP0IMIS_Pos)
#define	CCP_CCPMIS_PWMMIS5_Pos		(5)
#define CCP_CCPMIS_PWMMIS5_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS5_Pos)
#define	CCP_CCPMIS_PWMMIS4_Pos		(4)
#define CCP_CCPMIS_PWMMIS4_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS4_Pos)
#define	CCP_CCPMIS_PWMMIS1_Pos		(1)
#define CCP_CCPMIS_PWMMIS1_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS1_Pos)
#define	CCP_CCPMIS_PWMMIS0_Pos		(0)
#define CCP_CCPMIS_PWMMIS0_Msk		(0x1UL<<CCP_CCPMIS_PWMMIS0_Pos)

/*------CCPICLR-------------------------------------------------------------*/
#define	CCP_CCPICLR_CAP3ICLR_Pos	(11)
#define CCP_CCPICLR_CAP3ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP3ICLR_Pos)
#define	CCP_CCPICLR_CAP2ICLR_Pos	(10)
#define CCP_CCPICLR_CAP2ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP2ICLR_Pos)
#define	CCP_CCPICLR_CAP1ICLR_Pos	(9)
#define CCP_CCPICLR_CAP1ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP1ICLR_Pos)
#define	CCP_CCPICLR_CAP0ICLR_Pos	(8)
#define CCP_CCPICLR_CAP0ICLR_Msk	(0x1UL<<CCP_CCPICLR_CAP0ICLR_Pos)
#define	CCP_CCPICLR_PWMMICLR5_Pos	(5)
#define CCP_CCPICLR_PWMMICLR5_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR5_Pos)
#define	CCP_CCPICLR_PWMMICLR4_Pos	(4)
#define CCP_CCPICLR_PWMMICLR4_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR4_Pos)
#define	CCP_CCPICLR_PWMMICLR1_Pos	(1)
#define CCP_CCPICLR_PWMMICLR1_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR1_Pos)
#define	CCP_CCPICLR_PWMMICLR0_Pos	(0)
#define CCP_CCPICLR_PWMMICLR0_Msk	(0x1UL<<CCP_CCPICLR_PWMMICLR0_Pos)
/*------CCPRUN-------------------------------------------------------------*/
#define	CCP_CCPRUN_CCPRUN1_Pos		(1)
#define CCP_CCPRUN_CCPRUN1_Msk		(0x1UL<<CCP_CCPRUN_CCPRUN1_Pos)
#define	CCP_CCPRUN_CCPRUN0_Pos		(0)
#define CCP_CCPRUN_CCPRUN0_Msk		(0x1UL<<CCP_CCPRUN_CCPRUN0_Pos)
/*------CAPCON-------------------------------------------------------------*/
#define	CCP_CAPCON_CAPEN2_Pos		(13)
#define CCP_CAPCON_CAPEN2_Msk		(0x1UL<<CCP_CAPCON_CAPEN2_Pos)
#define	CCP_CAPCON_CAPEN_Pos		(12)
#define CCP_CAPCON_CAPEN_Msk		(0x1UL<<CCP_CAPCON_CAPEN_Pos)
#define	CCP_CAPCON_CAP3RLEN_Pos		(11)
#define CCP_CAPCON_CAP3RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP3RLEN_Pos)
#define	CCP_CAPCON_CAP2RLEN_Pos		(10)
#define CCP_CAPCON_CAP2RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP2RLEN_Pos)
#define	CCP_CAPCON_CAP1RLEN_Pos		(9)
#define CCP_CAPCON_CAP1RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP1RLEN_Pos)
#define	CCP_CAPCON_CAP0RLEN_Pos		(8)
#define CCP_CAPCON_CAP0RLEN_Msk		(0x1UL<<CCP_CAPCON_CAP0RLEN_Pos)
#define	CCP_CAPCON_CAP3ES_Pos		(6)
#define CCP_CAPCON_CAP3ES_Msk		(0x3UL<<CCP_CAPCON_CAP3ES_Pos)
#define	CCP_CAPCON_CAP2ES_Pos		(4)
#define CCP_CAPCON_CAP2ES_Msk		(0x3UL<<CCP_CAPCON_CAP2ES_Pos)
#define	CCP_CAPCON_CAP1ES_Pos		(2)
#define CCP_CAPCON_CAP1ES_Msk		(0x3UL<<CCP_CAPCON_CAP1ES_Pos)
#define	CCP_CAPCON_CAP0ES_Pos		(0)
#define CCP_CAPCON_CAP0ES_Msk		(0x3UL<<CCP_CAPCON_CAP0ES_Pos)
/*------CAPCHS-------------------------------------------------------------*/
#define	CCP_CAPCHS_ECAPS_Pos		(16)
#define CCP_CAPCHS_ECAPS_Msk		(0x1UL<<CCP_CAPCHS_ECAPS_Pos)
#define	CCP_CAPCHS_CAP3CHS_Pos		(12)
#define CCP_CAPCHS_CAP3CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP3CHS_Pos)
#define	CCP_CAPCHS_CAP2CHS_Pos		(8)
#define CCP_CAPCHS_CAP2CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP2CHS_Pos)
#define	CCP_CAPCHS_CAP1CHS_Pos		(4)
#define CCP_CAPCHS_CAP1CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP1CHS_Pos)
#define	CCP_CAPCHS_CAP0CHS_Pos		(0)
#define CCP_CAPCHS_CAP0CHS_Msk		(0xfUL<<CCP_CAPCHS_CAP0CHS_Pos)
/*------CAP0DAT-------------------------------------------------------------*/
#define	CCP_CAP0DAT_CAP_Pos			(16)
#define CCP_CAP0DAT_CAP_Msk			(0xffffUL<<CCP_CAP0DAT_CAP_Pos)
#define	CCP_CAP0DAT_DAT_Pos			(0)
#define CCP_CAP0DAT_DAT_Msk			(0xffffUL<<CCP_CAP0DAT_DAT_Pos)
/*------CAP1DAT-------------------------------------------------------------*/
#define	CCP_CAP1DAT_CAP_Pos			(16)
#define CCP_CAP1DAT_CAP_Msk			(0xffffUL<<CCP_CAP1DAT_CAP_Pos)
#define	CCP_CAP1DAT_DAT_Pos			(0)
#define CCP_CAP1DAT_DAT_Msk			(0xffffUL<<CCP_CAP1DAT_DAT_Pos)
/*------CAP2DAT-------------------------------------------------------------*/
#define	CCP_CAP2DAT_CAP_Pos			(16)
#define CCP_CAP2DAT_CAP_Msk			(0xffffUL<<CCP_CAP2DAT_CAP_Pos)
#define	CCP_CAP2DAT_DAT_Pos			(0)
#define CCP_CAP2DAT_DAT_Msk			(0xffffUL<<CCP_CAP2DAT_DAT_Pos)
/*------CAP3DAT-------------------------------------------------------------*/
#define	CCP_CAP3DAT_CAP_Pos			(16)
#define CCP_CAP3DAT_CAP_Msk			(0xffffUL<<CCP_CAP3DAT_CAP_Pos)
#define	CCP_CAP3DAT_DAT_Pos			(0)
#define CCP_CAP3DAT_DAT_Msk			(0xffffUL<<CCP_CAP3DAT_DAT_Pos)

/*---------------------- UART  Manger Controller -------------------------*/
typedef struct
{					
	__I  uint32_t RBR;
	__O  uint32_t THR;
	__IO uint32_t DLR;
	__IO uint32_t IER;
	__I  uint32_t IIR;
	__O  uint32_t FCR;
	__IO uint32_t LCR;
	__IO uint32_t MCR;
	__I  uint32_t LSR;
	__I  uint32_t MSR;
	__IO uint32_t SCR;
	__IO uint32_t EFR;
	__IO uint32_t XON1;
	__IO uint32_t XON2;
	__IO uint32_t XOFF1;
	__IO uint32_t XOFF2;
} UART_T;
/*------IER----------------------------------------------------------*/
#define	UART_IER_CTSIE_Pos				(7)
#define UART_IER_CTSIE_Msk				(0x1UL<<UART_IER_CTSIE_Pos)
#define	UART_IER_RTSIE_Pos				(6)
#define UART_IER_RTSIE_Msk				(0x1UL<<UART_IER_RTSIE_Pos)
#define	UART_IER_XOFIE_Pos				(5)
#define UART_IER_XOFIE_Msk				(0x1UL<<UART_IER_XOFIE_Pos)
#define	UART_IER_MDSIE_Pos				(3)
#define UART_IER_MDSIE_Msk				(0x1UL<<UART_IER_MDSIE_Pos)
#define	UART_IER_RLSIE_Pos				(2)
#define UART_IER_RLSIE_Msk				(0x1UL<<UART_IER_RLSIE_Pos)
#define	UART_IER_THREIE_Pos				(1)
#define UART_IER_THREIE_Msk				(0x1UL<<UART_IER_THREIE_Pos)
#define	UART_IER_RBREIE_Pos				(0)
#define UART_IER_RBREIE_Msk				(0x1UL<<UART_IER_RBREIE_Pos)

/*------IIR----------------------------------------------------------*/
#define	UART_IIR_INTHFC_Pos				(5)
#define UART_IIR_INTHFC_Msk				(0x1UL<<UART_IIR_INTHFC_Pos)
#define	UART_IIR_INTSFC_Pos				(4)
#define UART_IIR_INTSFC_Msk				(0x1UL<<UART_IIR_INTSFC_Pos)
#define	UART_IIR_INTID_Pos				(1)
#define UART_IIR_INTID_Msk				(0x7UL<<UART_IIR_INTID_Pos)
#define	UART_IIR_INTSTATUS_Pos			(0)
#define UART_IIR_INTSTATUS_Msk			(0x1UL<<UART_IIR_INTSTATUS_Pos)
/*------FCR----------------------------------------------------------*/
#define	UART_FCR_RXTL_Pos				(6)
#define UART_FCR_RXTL_Msk				(0x3UL<<UART_FCR_RXTL_Pos)
#define	UART_FCR_TXTL_Pos				(4)
#define UART_FCR_TXTL_Msk				(0x3UL<<UART_FCR_TXTL_Pos)
#define	UART_FCR_TXFIFORST_Pos			(2)
#define UART_FCR_TXFIFORST_Msk			(0x1UL<<UART_FCR_TXFIFORST_Pos)
#define	UART_FCR_RXFIFORST_Pos			(1)
#define UART_FCR_RXFIFORST_Msk			(0x1UL<<UART_FCR_RXFIFORST_Pos)
#define	UART_FCR_FIFOEN_Pos				(0)
#define UART_FCR_FIFOEN_Msk				(0x1UL<<UART_FCR_FIFOEN_Pos)

/*------LCR----------------------------------------------------------*/
#define	UART_LCR_BCON_Pos				(6)
#define UART_LCR_BCON_Msk				(0x1UL<<UART_LCR_BCON_Pos)
#define	UART_LCR_PSEL_Pos				(4)
#define UART_LCR_PSEL_Msk				(0x3UL<<UART_LCR_PSEL_Pos)
#define	UART_LCR_PEN_Pos				(3)
#define UART_LCR_PEN_Msk				(0x1UL<<UART_LCR_PEN_Pos)
#define	UART_LCR_SBS_Pos				(2)
#define UART_LCR_SBS_Msk				(0x1UL<<UART_LCR_SBS_Pos)
#define	UART_LCR_WLS_Pos				(0)
#define UART_LCR_WLS_Msk				(0x3UL<<UART_LCR_WLS_Pos)

/*------MCR----------------------------------------------------------*/
#define	UART_MCR_XOFFS_Pos				(7)
#define UART_MCR_XOFFS_Msk				(0x1UL<<UART_MCR_XOFFS_Pos)
#define	UART_MCR_IREN_Pos				(6)
#define UART_MCR_IREN_Msk				(0x1UL<<UART_MCR_IREN_Pos)
#define	UART_MCR_MLBM_Pos				(4)
#define UART_MCR_MLBM_Msk				(0x1UL<<UART_MCR_MLBM_Pos)
#define	UART_MCR_RTS_Pos				(1)
#define UART_MCR_RTS_Msk				(0x1UL<<UART_MCR_RTS_Pos)

/*------LSR----------------------------------------------------------*/
#define	UART_LSR_RXFE_Pos				(7)
#define UART_LSR_RXFE_Msk				(0x1UL<<UART_LSR_RXFE_Pos)
#define	UART_LSR_TEMT_Pos				(6)
#define UART_LSR_TEMT_Msk				(0x1UL<<UART_LSR_TEMT_Pos)
#define	UART_LSR_THRE_Pos				(5)
#define UART_LSR_THRE_Msk				(0x1UL<<UART_LSR_THRE_Pos)
#define	UART_LSR_BI_Pos					(4)
#define UART_LSR_BI_Msk					(0x1UL<<UART_LSR_BI_Pos)
#define	UART_LSR_FE_Pos					(3)
#define UART_LSR_FE_Msk					(0x1UL<<UART_LSR_FE_Pos)
#define	UART_LSR_PE_Pos					(2)
#define UART_LSR_PE_Msk					(0x1UL<<UART_LSR_PE_Pos)
#define	UART_LSR_OE_Pos					(1)
#define UART_LSR_OE_Msk					(0x1UL<<UART_LSR_OE_Pos)
#define	UART_LSR_RDR_Pos				(0)
#define UART_LSR_RDR_Msk				(0x1UL<<UART_LSR_RDR_Pos)

/*------MSR----------------------------------------------------------*/
#define	UART_MSR_CTS_Pos				(4)
#define UART_MSR_CTS_Msk				(0x1UL<<UART_MSR_CTS_Pos)
#define	UART_MSR_DCTS_Pos				(0)
#define UART_MSR_DCTS_Msk				(0x1UL<<UART_MSR_DCTS_Pos)

/*------EFR----------------------------------------------------------*/
#define	UART_EFR_AUTOCTS_Pos			(7)
#define UART_EFR_AUTOCTS_Msk			(0x1UL<<UART_EFR_AUTOCTS_Pos)
#define	UART_EFR_AUTORTS_Pos			(6)
#define UART_EFR_AUTORTS_Msk			(0x1UL<<UART_EFR_AUTORTS_Pos)
#define	UART_EFR_AUTOIEN_Pos			(4)
#define UART_EFR_AUTOIEN_Msk			(0x1UL<<UART_EFR_AUTOIEN_Pos)
#define	UART_EFR_TXSWFC_Pos				(2)
#define UART_EFR_TXSWFC_Msk				(0x3UL<<UART_EFR_TXSWFC_Pos)
#define	UART_EFR_RXSWFC_Pos				(0)
#define UART_EFR_RXSWFC_Msk				(0x3UL<<UART_EFR_RXSWFC_Pos)


/*---------------------- I2C  Manger Controller -------------------------*/
typedef struct
{					
	__IO  uint32_t CONSET;
	__IO  uint32_t CONCLR;
	__IO  uint32_t STAT;
	__IO  uint32_t DAT;
	__IO  uint32_t CLK;
	__IO  uint32_t ADR0;
	__IO  uint32_t ADM0;
	__IO  uint32_t XADR0;
	__IO  uint32_t XADM0;
	__IO  uint32_t RST;
	__IO  uint32_t ADR1;
	__IO  uint32_t ADM1;
	__IO  uint32_t ADR2;
	__IO  uint32_t ADM2;
	__IO  uint32_t ADR3;
	__IO  uint32_t ADM3;
} I2C_T;

/*------CONSET---------------------------------------------------------------*/
#define	I2C_CONSSET_GCF_Pos				(8)
#define I2C_CONSSET_GCF_Msk				(0x1UL<<I2C_CONSSET_GCF_Pos)
#define	I2C_CONSSET_I2CIE_Pos			(7)
#define I2C_CONSSET_I2CIE_Msk			(0x1UL<<I2C_CONSSET_I2CIE_Pos)
#define	I2C_CONSSET_I2CEN_Pos			(6)
#define I2C_CONSSET_I2CEN_Msk			(0x1UL<<I2C_CONSSET_I2CEN_Pos)
#define	I2C_CONSSET_STA_Pos				(5)
#define I2C_CONSSET_STA_Msk				(0x1UL<<I2C_CONSSET_STA_Pos)
#define	I2C_CONSSET_STO_Pos				(4)
#define I2C_CONSSET_STO_Msk				(0x1UL<<I2C_CONSSET_STO_Pos)
#define	I2C_CONSSET_SI_Pos				(3)
#define I2C_CONSSET_SI_Msk				(0x1UL<<I2C_CONSSET_SI_Pos)
#define	I2C_CONSSET_AA_Pos				(2)
#define I2C_CONSSET_AA_Msk				(0x1UL<<I2C_CONSSET_AA_Pos)
#define	I2C_CONSSET_XADRF_Pos			(1)
#define I2C_CONSSET_XADRF_Msk			(0x1UL<<I2C_CONSSET_XADRF_Pos)
#define	I2C_CONSSET_ADRF_Pos			(0)
#define I2C_CONSSET_ADRF_Msk			(0x1UL<<I2C_CONSSET_ADRF_Pos)
/*------CONCLR---------------------------------------------------------------*/
#define	I2C_CONSCLR_I2CIEC_Pos			(7)
#define I2C_CONSCLR_I2CIEC_Msk			(0x1UL<<I2C_CONSCLR_I2CIEC_Pos)
#define	I2C_CONSCLR_I2CENC_Pos			(6)
#define I2C_CONSCLR_I2CEMC_Msk			(0x1UL<<I2C_CONSCLR_I2CENC_Pos)
#define	I2C_CONSCLR_STAC_Pos			(5)
#define I2C_CONSCLR_STAC_Msk			(0x1UL<<I2C_CONSCLR_STAC_Pos)
#define	I2C_CONSCLR_SIC_Pos				(3)
#define I2C_CONSCLR_SIC_Msk				(0x1UL<<I2C_CONSCLR_SIC_Pos)
#define	I2C_CONSCLR_AAC_Pos				(2)
#define I2C_CONSCLR_AAC_Msk				(0x1UL<<I2C_CONSCLR_AAC_Pos)
/*------STAT---------------------------------------------------------------*/
#define	I2C_STAT_STATUS_Pos				(0)
#define I2C_STAT_STATUS_Msk				(0xFFUL<<I2C_STAT_STATUS_Pos)





/*---------------------- SPP/SPI  Manger Controller ----------------------*/
typedef struct
{					
	__IO  uint32_t CON;
	__I   uint32_t STAT;
	__IO  uint32_t DAT;
	__IO  uint32_t CLK;
	__IO  uint32_t IMSC;
	__I   uint32_t RIS;
	__I   uint32_t MIS;
	__O   uint32_t ICLR;
	__I  uint32_t RESERVE[2];	
	__IO  uint32_t CSCR;
} SSP_T;

/*------CON---------------------------------------------------------------*/
#define	SSP_CON_LBM_Pos				(11)
#define SSP_CON_LBM_Msk				(0x1UL<<SSP_CON_LBM_Pos)
#define	SSP_CON_SSPEN_Pos			(10)
#define SSP_CON_SSPEN_Msk			(0x1UL<<SSP_CON_SSPEN_Pos)
#define	SSP_CON_MS_Pos				(9)
#define SSP_CON_MS_Msk				(0x1UL<<SSP_CON_MS_Pos)
#define	SSP_CON_SOD_Pos				(8)
#define SSP_CON_SOD_Msk				(0x1UL<<SSP_CON_SOD_Pos)
#define	SSP_CON_CPH_Pos				(7)
#define SSP_CON_CPH_Msk				(0x1UL<<SSP_CON_CPH_Pos)
#define	SSP_CON_CPO_Pos				(6)
#define SSP_CON_CPO_Msk				(0x1UL<<SSP_CON_CPO_Pos)
#define	SSP_CON_FRF_Pos				(4)
#define SSP_CON_FRF_Msk				(0x3UL<<SSP_CON_FRF_Pos)
#define	SSP_CON_DSS_Pos				(0)
#define SSP_CON_DSS_Msk				(0xFUL<<SSP_CON_DSS_Pos)
/*------STAT---------------------------------------------------------------*/
#define	SSP_STAT_BSY_Pos			(4)
#define SSP_STAT_BSY_Msk			(0x1UL<<SSP_STAT_BSY_Pos)
#define	SSP_STAT_RFF_Pos			(3)
#define SSP_STAT_RFF_Msk			(0x1UL<<SSP_STAT_RFF_Pos)
#define	SSP_STAT_RNE_Pos			(2)
#define SSP_STAT_RNE_Msk			(0x1UL<<SSP_STAT_RNE_Pos)
#define	SSP_STAT_TNF_Pos			(1)
#define SSP_STAT_TNF_Msk			(0x1UL<<SSP_STAT_TNF_Pos)
#define	SSP_STAT_TFE_Pos			(0)
#define SSP_STAT_TFE_Msk			(0x1UL<<SSP_STAT_TFE_Pos)
/*------CSCR---------------------------------------------------------------*/
#define	SSP_CSCR_SPH_Pos			(4)
#define SSP_CSCR_SPH_Msk			(0x1UL<<SSP_CSCR_SPH_Pos)
#define	SSP_CSCR_SWCS_Pos			(3)
#define SSP_CSCR_SWCS_Msk			(0x1UL<<SSP_CSCR_SWCS_Pos)
#define	SSP_CSCR_SWSEL_Pos			(2)
#define SSP_CSCR_SWSEL_Msk			(0x1UL<<SSP_CSCR_SWSEL_Pos)

/*---------------------- ADCB  Manger Controller -------------------------*/
typedef struct
{					
	__IO  uint32_t CON;
	__IO  uint32_t CON2;
	__IO  uint32_t HWTG;
	__I   uint32_t RESERVE2[1];
	__IO  uint32_t SCAN;
	__IO  uint32_t CMP[2];
	__IO  uint32_t IMSC;
	__I   uint32_t RIS;
	__I   uint32_t MIS;
	__O   uint32_t ICLR;
	__IO  uint32_t LOCK;
	__I   uint32_t RESERVE3[3];
	__I   uint32_t RESERVE0[3];
	__IO  uint32_t TEST;	
	__I   uint32_t RESERVE1[13];	
	__I   uint32_t DATA[30];
} ADCB_T;

/*------CON----------------------------------------------------------------*/
#define	ADCB_CON_ADCRST_Pos				(31)
#define ADCB_CON_ADCRST_Msk				(0x1UL<<ADCB_CON_ADCRST_Pos)
#define	ADCB_CON_ADMODE10_Pos			(24)
#define ADCB_CON_ADMODE10_Msk			(0x3UL<<ADCB_CON_ADMODE10_Pos)
#define	ADCB_CON_ADCNSMP_Pos			(16)
#define ADCB_CON_ADCNSMP_Msk			(0xffUL<<ADCB_CON_ADCNSMP_Pos)
#define	ADCB_CON_ADCSWCHE_Pos			(13)
#define ADCB_CON_ADCSWCHE_Msk			(0x1UL<<ADCB_CON_ADCSWCHE_Pos)
#define	ADCB_CON_ADCNDISEN_Pos			(12)
#define ADCB_CON_ADCNDISEN_Msk			(0x1UL<<ADCB_CON_ADCNDISEN_Pos)
#define	ADCB_CON_ADCNDISTS_Pos			(8)
#define ADCB_CON_ADCNDISTS_Msk			(0xFUL<<ADCB_CON_ADCNDISTS_Pos)
#define	ADCB_CON_ADCVS_Pos				(6)
#define ADCB_CON_ADCVS_Msk				(0x3UL<<ADCB_CON_ADCVS_Pos)
#define	ADCB_CON_ADCVG_Pos				(5)
#define ADCB_CON_ADCVG_Msk				(0x1UL<<ADCB_CON_ADCVG_Pos)
#define	ADCB_CON_ADCEN_Pos				(4)
#define ADCB_CON_ADCEN_Msk				(0x1UL<<ADCB_CON_ADCEN_Pos)
#define	ADCB_CON_ADCMS_Pos				(3)
#define ADCB_CON_ADCMS_Msk				(0x1UL<<ADCB_CON_ADCMS_Pos)
#define	ADCB_CON_ADCDIV_Pos				(0)
#define ADCB_CON_ADCDIV_Msk				(0x7UL<<ADCB_CON_ADCDIV_Pos)

/*------CON2----------------------------------------------------------------*/
#define	ADCB_CON2_ADCICHS_Pos			(13)
#define ADCB_CON2_ADCICHS_Msk			(0x7UL<<ADCB_CON2_ADCICHS_Pos)
#define	ADCB_CON2_ADCSF4_Pos			(12)
#define ADCB_CON2_ADCSF4_Msk			(0x1UL<<ADCB_CON2_ADCSF4_Pos)
#define	ADCB_CON2_ADCSF3_Pos			(11)
#define ADCB_CON2_ADCSF3_Msk			(0x1UL<<ADCB_CON2_ADCSF3_Pos)
#define	ADCB_CON2_ADCSF2_Pos			(10)
#define ADCB_CON2_ADCSF2_Msk			(0x1UL<<ADCB_CON2_ADCSF2_Pos)
#define	ADCB_CON2_ADCSF1_Pos			(9)
#define ADCB_CON2_ADCSF1_Msk			(0x1UL<<ADCB_CON2_ADCSF1_Pos)
#define	ADCB_CON2_ADCSF0_Pos			(8)
#define ADCB_CON2_ADCSF0_Msk			(0x1UL<<ADCB_CON2_ADCSF0_Pos)
#define	ADCB_CON2_ADCST_Pos				(7)
#define ADCB_CON2_ADCST_Msk				(0x1UL<<ADCB_CON2_ADCST_Pos)
#define	ADCB_CON2_ADCSMPWAIT_Pos		(6)
#define ADCB_CON2_ADCSMPWAIT_Msk		(0x1UL<<ADCB_CON2_ADCSMPWAIT_Pos)
#define	ADCB_CON2_ADCSWCHS_Pos			(0)
#define ADCB_CON2_ADCSWCHS_Msk			(0x1FUL<<ADCB_CON2_ADCSWCHS_Pos)

/*------HWTG----------------------------------------------------------------*/
#define	ADCB_HWTG_ADCINTTGEN_Pos		(15)
#define ADCB_HWTG_ADCINTTGEN_Msk		(0x1UL<<ADCB_HWTG_ADCINTTGEN_Pos)
#define	ADCB_HWTG_ADCINTTGSS_Pos		(12)
#define ADCB_HWTG_ADCINTTGSS_Msk		(0x7UL<<ADCB_HWTG_ADCINTTGSS_Pos)

/*------CMP----------------------------------------------------------------*/
#define	ADCB_CMP_ADCCMPEN_Pos			(31)
#define ADCB_CMP_ADCCMPEN_Msk			(0x1UL<<ADCB_CMP_ADCCMPEN_Pos)
#define	ADCB_CMP_ADCCMPO_Pos			(30)
#define ADCB_CMP_ADCCMPO_Msk			(0x1UL<<ADCB_CMP_ADCCMPO_Pos)
#define	ADCB_CMP_ADCCMPCOND_Pos			(28)
#define ADCB_CMP_ADCCMPCOND_Msk			(0x1UL<<ADCB_CMP_ADCCMPCOND_Pos)
#define	ADCB_CMP_ADCCMPMCNT_Pos			(24)
#define ADCB_CMP_ADCCMPMCNT_Msk			(0xFUL<<ADCB_CMP_ADCCMPMCNT_Pos)
#define	ADCB_CMP_ADCCMPCHS_Pos			(16)
#define ADCB_CMP_ADCCMPCHS_Msk			(0x1FUL<<ADCB_CMP_ADCCMPCHS_Pos)
#define	ADCB_CMP_ADCCMPDATA_Pos			(0)
#define ADCB_CMP_ADCCMPDATA_Msk			(0xFFFUL<<ADCB_CMP_ADCCMPCHS_Pos)
/*------TEST----------------------------------------------------------------*/
#define	ADCB_TEST_ADCSWT_Pos			(24)
#define ADCB_TEST_ADCSWT_Msk			(0xFFUL<<ADCB_TEST_ADCSWT_Pos)

/*------IMSC----------------------------------------------------------------*/
#define	ADCB_IMSC_IMSC31_Pos			(31)
#define ADCB_IMSC_IMSC31_Msk			(0x1UL<<ADCB_IMSC_IMSC31_Pos)
/*------RIS-----------------------------------------------------------------*/
#define	ADCB_RIS_RIS31_Pos				(31)
#define ADCB_RIS_RIS31_Msk				(0x1UL<<ADCB_RIS_RIS31_Pos)
/*------MIS-----------------------------------------------------------------*/
#define	ADCB_MIS_MIS31_Pos				(31)
#define ADCB_MIS_MIS31_Msk				(0x1UL<<ADCB_MIS_MIS31_Pos)
/*------ICLR----------------------------------------------------------------*/
#define	ADCB_ICLR_ICLR31_Pos			(31)
#define ADCB_ICLR_ICLR31_Msk			(0x1UL<<ADCB_ICLR_ICLR31_Pos)

/*---------------------- ACMP Manger Controller -------------------------*/
typedef struct
{					
	__IO  uint32_t C0CON0;
	__IO  uint32_t C0CON1;
	__IO  uint32_t C0CON2;
	__I   uint32_t RESERVE0[1];
	__IO  uint32_t C1CON0;
	__IO  uint32_t C1CON1;
	__IO  uint32_t C1CON2;
	__I   uint32_t RESERVE1[1];
	__IO  uint32_t CVRCON;
	__I   uint32_t RESERVE2[1];
	__IO  uint32_t IMSC;
	__I   uint32_t RIS;
	__I   uint32_t MIS;
	__O   uint32_t ICLR;
	__IO  uint32_t LOCK;
} ACMP_T;

/*------C0CON0----------------------------------------------------------------*/
#define	ACMP_C0CON0_EN_Pos					(15)
#define ACMP_C0CON0_EN_Msk					(0x1UL<<ACMP_C0CON0_EN_Pos)
#define	ACMP_C0CON0_COFM_Pos				(14)
#define ACMP_C0CON0_COFM_Msk				(0x1UL<<ACMP_C0CON0_COFM_Pos)
#define	ACMP_C0CON0_N2GND_Pos				(13)
#define ACMP_C0CON0_N2GND_Msk				(0x1UL<<ACMP_C0CON0_N2GND_Pos)
#define	ACMP_C0CON0_PS_Pos					(4)
#define ACMP_C0CON0_PS_Msk					(0x7UL<<ACMP_C0CON0_PS_Pos)
#define	ACMP_C0CON0_NS_Pos					(0)
#define ACMP_C0CON0_NS_Msk					(0x3UL<<ACMP_C0CON0_NS_Pos)
/*------C0CON1----------------------------------------------------------------*/
#define	ACMP_C0CON1_OUT_Pos					(9)
#define ACMP_C0CON1_OUT_Msk					(0x1UL<<ACMP_C0CON1_OUT_Pos)
/*------C0CON2----------------------------------------------------------------*/
#define	ACMP_C0CON2_HYSLS_Pos				(12)
#define ACMP_C0CON2_HYSLS_Msk				(0x3UL<<ACMP_C0CON2_HYSLS_Pos)
#define	ACMP_C0CON2_HYSVS_Pos				(10)
#define ACMP_C0CON2_HYSVS_Msk				(0x3UL<<ACMP_C0CON2_HYSVS_Pos)
#define	ACMP_C0CON2_POS_Pos					(9)
#define ACMP_C0CON2_POS_Msk					(0x1UL<<ACMP_C0CON2_POS_Pos)
#define	ACMP_C0CON2_FE_Pos					(8)
#define ACMP_C0CON2_FE_Msk					(0x1UL<<ACMP_C0CON2_FE_Pos)
#define	ACMP_C0CON2_FS_Pos					(0)
#define ACMP_C0CON2_FS_Msk					(0xFUL<<ACMP_C0CON2_FS_Pos)

/*------C1CON0----------------------------------------------------------------*/
#define	ACMP_C1CON0_EN_Pos					(15)
#define ACMP_C1CON0_EN_Msk					(0x1UL<<ACMP_C1CON0_EN_Pos)
#define	ACMP_C1CON0_COFM_Pos				(14)
#define ACMP_C1CON0_COFM_Msk				(0x1UL<<ACMP_C1CON0_COFM_Pos)
#define	ACMP_C1CON0_N2GND_Pos				(13)
#define ACMP_C1CON0_N2GND_Msk				(0x1UL<<ACMP_C1CON0_N2GND_Pos)
#define	ACMP_C1CON0_C1P2SEL_Pos				(8)
#define ACMP_C1CON0_C1P2SEL_Msk				(0x1UL<<ACMP_C1CON0_C1P2SEL_Pos)
#define	ACMP_C1CON0_PS_Pos					(4)
#define ACMP_C1CON0_PS_Msk					(0x7UL<<ACMP_C1CON0_PS_Pos)
#define	ACMP_C1CON0_C1N1S_Pos				(2)
#define ACMP_C1CON0_C1N1S_Msk				(0x1UL<<ACMP_C1CON0_C1N1S_Pos)
#define	ACMP_C1CON0_NS_Pos					(0)
#define ACMP_C1CON0_NS_Msk					(0x3UL<<ACMP_C1CON0_NS_Pos)
/*------C1CON1----------------------------------------------------------------*/
#define	ACMP_C1CON1_OUT_Pos					(9)
#define ACMP_C1CON1_OUT_Msk					(0x1UL<<ACMP_C1CON1_OUT_Pos)

/*------C1CON2----------------------------------------------------------------*/
#define	ACMP_C1CON2_HYSLS_Pos				(12)
#define ACMP_C1CON2_HYSLS_Msk				(0x3UL<<ACMP_C1CON2_HYSLS_Pos)
#define	ACMP_C1CON2_HYSVS_Pos				(10)
#define ACMP_C1CON2_HYSVS_Msk				(0x3UL<<ACMP_C1CON2_HYSVS_Pos)
#define	ACMP_C1CON2_POS_Pos					(9)
#define ACMP_C1CON2_POS_Msk					(0x1UL<<ACMP_C1CON2_POS_Pos)
#define	ACMP_C1CON2_FE_Pos					(8)
#define ACMP_C1CON2_FE_Msk					(0x1UL<<ACMP_C1CON2_FE_Pos)
#define	ACMP_C1CON2_FS_Pos					(0)
#define ACMP_C1CON2_FS_Msk					(0xFUL<<ACMP_C1CON2_FS_Pos)

/*------CVRCON----------------------------------------------------------------*/
#define	ACMP_CVRCON_CSVR_Pos				(4)
#define ACMP_CVRCON_CSVR_Msk				(0x3UL<<ACMP_CVRCON_CSVR_Pos)
#define	ACMP_CVRCON_CVS_Pos					(0)
#define ACMP_CVRCON_CVS_Msk					(0xFUL<<ACMP_CVRCON_CVS_Pos)

/*------IMSC------------------------------------------------------------------*/
#define	ACMP_IMSC_C1IF_Pos					(1)
#define ACMP_IMSC_C1IF_Msk					(0x1UL<<ACMP_IMSC_C1IF_Pos)
#define	ACMP_IMSC_C0IF_Pos					(0)
#define ACMP_IMSC_C0IF_Msk					(0x1UL<<ACMP_IMSC_C0IF_Pos)
/*------RIS------------------------------------------------------------------*/
#define	ACMP_RIS_C1IF_Pos					(1)
#define ACMP_RIS_C1IF_Msk					(0x1UL<<ACMP_RIS_C1IF_Pos)
#define	ACMP_RIS_C0IF_Pos					(0)
#define ACMP_RIS_C0IF_Msk					(0x1UL<<ACMP_RIS_C0IF_Pos)
/*------MIS------------------------------------------------------------------*/
#define	ACMP_MIS_C1IF_Pos					(1)
#define ACMP_MIS_C1IF_Msk					(0x1UL<<ACMP_MIS_C1IF_Pos)
#define	ACMP_MIS_C0IF_Pos					(0)
#define ACMP_MIS_C0IF_Msk					(0x1UL<<ACMP_MIS_C0IF_Pos)
/*------ICLR------------------------------------------------------------------*/
#define	ACMP_ICLR_C1IF_Pos					(1)
#define ACMP_ICLR_C1IF_Msk					(0x1UL<<ACMP_ICLR_C1IF_Pos)
#define	ACMP_ICLR_C0IF_Pos					(0)
#define ACMP_ICLR_C0IF_Msk					(0x1UL<<ACMP_ICLR_C0IF_Pos)


/*---------------------- FMC Manger Controller -------------------------*/
typedef struct
{					
	__IO  uint32_t CON;
	__IO  uint32_t ADR;
	__IO  uint32_t DAT;
	__IO  uint32_t CMD;
	__IO  uint32_t LOCK;
	__I   uint32_t RESERVE[3];
	__IO  uint32_t CRCEA;
	__IO  uint32_t CRCIN;
	__IO  uint32_t CRCD;
} FMC_T;

/*------CON------------------------------------------------------------------*/
#define	FMC_CON_BUSY_Pos					(5)
#define FMC_CON_BUSY_Msk					(0x1UL<<FMC_CON_BUSY_Pos)
#define	FMC_CON_ISPS_Pos					(4)
#define FMC_CON_ISPS_Msk					(0x1UL<<FMC_CON_ISPS_Pos)


/*---------------------- UID Manger Controller -------------------------*/
typedef struct
{					
	__I   uint32_t UID0;
	__I   uint32_t UID1;
	__I   uint32_t UID2;
} UID_T;


/*@}*/ /* end of REGISTER  group  Peripherals */

/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/
/** @addtogroup   Memory Mapped Structure for Peripheral
  @{
*/
/* Peripheral and SRAM base address */
#define FLASH_BASE          (0x00000000UL)        /*!< (FLASH   ) Base Address */
#define INFO_BASE           (0x10000000UL)        /*!< (INFO    ) Base Address */
#define SRAM_BASE           (0x20000000UL)        /*!< (SRAM    ) Base Address */
#define APB_BASE            (0x40000000UL)        /*!< (APB     ) Base Address */
#define AHB_BASE            (0x50000000UL)        /*!< (AHB     ) Base Address */
#define UID_BASE            (0x18000004UL)        /*!< (UID    ) Base Address */
 
/* APB memory map */
#define WWDT_BASE           (APB_BASE + 0x1800000UL)  
#define CCP_BASE            (APB_BASE + 0x2800000UL)    
#define SSP_BASE            (APB_BASE + 0x3800000UL)  
#define UART0_BASE          (APB_BASE + 0x4800000UL)  
#define UART1_BASE          (APB_BASE + 0x5000000UL)  
#define TMR0_BASE           (APB_BASE + 0x6800000UL)  
#define TMR1_BASE           (APB_BASE + 0x6800100UL)  
#define TMR2_BASE           (APB_BASE + 0x7000000UL)  
#define TMR3_BASE           (APB_BASE + 0x7000100UL)  
#define WDT_BASE            (APB_BASE + 0x7800000UL)  
#define I2C_BASE            (APB_BASE + 0x8000000UL)  
#define FMC_BASE            (APB_BASE + 0x9800000UL) 
#define CRC_BASE            (APB_BASE + 0xA000000UL) 
#define ACMP_BASE           (APB_BASE + 0xD000000UL) 
#define ADCB_BASE           (APB_BASE + 0xD800000UL) 
/* AHB memory map */
#define SYSCON_BASE         (AHB_BASE) 
#define GPIO0_BASE          (AHB_BASE + 0x2000000UL) 
#define GPIO1_BASE          (AHB_BASE + 0x2800000UL) 
#define GPIO2_BASE          (AHB_BASE + 0x3000000UL) 
#define GPIO3_BASE          (AHB_BASE + 0x3800000UL) 
#define GPIO4_BASE          (AHB_BASE + 0x4000000UL) 
#define DIV_BASE            (AHB_BASE + 0x5000000UL) 

/*@}*/ /* end of group  MemoryMap */

/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/
/** @addtogroup  PeripheralDecl  Peripheral Declaration
  @{
*/
#define WWDT				((WWDT_T  	*)	WWDT_BASE) 
#define CCP					((CCP_T		*)	CCP_BASE) 
#define SSP					((SSP_T		*)	SSP_BASE)
#define UART0				((UART_T	*)	UART0_BASE) 
#define UART1				((UART_T	*)	UART1_BASE) 
#define TMR0				((TMR_T		*)	TMR0_BASE) 
#define TMR1				((TMR_T		*)	TMR1_BASE) 
#define TMR2				((TMR_T		*)	TMR2_BASE) 
#define TMR3				((TMR_T		*)	TMR3_BASE) 
#define WDT					((WDT_T		*)	WDT_BASE) 
#define I2C					((I2C_T		*)	I2C_BASE) 
#define FMC					((FMC_T		*)	FMC_BASE) 
#define CRC					((CRC_T		*)	CRC_BASE) 
#define ACMP                ((ACMP_T	*)	ACMP_BASE)
#define ADCB                ((ADCB_T	*)	ADCB_BASE)
#define SYS                 ((SYS_T		*)	SYSCON_BASE)
#define GPIO0               ((GPIO_T	*)	GPIO0_BASE)
#define GPIO1               ((GPIO_T	*)	GPIO1_BASE)
#define GPIO2               ((GPIO_T	*)	GPIO2_BASE)
#define GPIO3               ((GPIO_T	*)	GPIO3_BASE)
#define GPIO4               ((GPIO_T	*)	GPIO4_BASE)
#define DIV				((DIV_T	*)	DIV_BASE)
#define UID					((UID_T	*)		UID_BASE)





/******************************************************************************/
/*                         Peripheral header files                            */
/******************************************************************************/
#include "system.h"
#include "gpio.h"
#include "wdt.h"
#include "wwdt.h"
#include "crc.h"
#include "i2c.h"
#include "ssp.h"
#include "timer.h"
#include "uart.h"
#include "ccp.h"
#include "divsqrt.h"
#include "adc.h"
#include "fmc.h"
#include "acmp.h"


/*****************************************************************************/
/* Global type definitions ('typedef') */
/*****************************************************************************/


/*****************************************************************************/
/* Global variable declarations ('extern', definition in C source) */
/*****************************************************************************/


/*****************************************************************************/
/* Global function prototypes ('extern', definition in C source) */
/*****************************************************************************/

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

#ifdef __cplusplus
}
#endif

#endif /* __CMS32M56XXX_H__ */






